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cy23fs04 failsafe? 2.5 v/3.3 v zero delay buffer cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-07304 rev. *h revised august 8, 2012 features internal digital controlled crystal oscillator (dcxo) for continuous glitch-free operation zero input-output propagation delay low jitter (35 ps max rms) outputs low output-to-output skew (200 ps max) 4.17 mhz to 166.7 mhz reference input supports industry standard input crystals 166.7 mhz outputs 5 v tolerant inputs phase-locked loop (pll) bypass mode dual reference inputs 16-pin thin shrunk small outline package (tssop) 2.5 v or 3.3 v output power supplies 3.3 v core power supply industrial temperature range functional description the cy23fs04 is a failsafe ? zero delay buffer with two reference clock inputs and four phase-aligned outputs. the device provides an optimum solution for applications where continuous operation is required in the event of a primary clock failure. the continuous, glitch-free oper ation is achieved by using a dcxo. this serves as a redundant clock source in the event of a reference clock failure by maintaining the last frequency and phase information of the reference clock. the unique feature of the cy23fs04 is that the dcxo is the primary clocking source, which is synchronized (phase-aligned) to the external reference clock. when this external clock is restored, the dcxo automatically resynchronizes to the external clock. the frequency of the crystal that is connected to the dcxo must be an integer factor of the fre quency of the reference clock. this factor is set by two select lines: s[2:1], see ta b l e 2 on page 3. the output power supply v dd can be connected to either 2.5 v or 3.3 v. vddc is the power supply pin for internal circuits and must be connected to 3.3 v. clka[2:1] clkb[2:1] dcxo decoder 2 failsafe tm block pll xin xout 2 2 ref2 fbk s[2:1] fail# /safe ref1 refsel logic block diagram
cy23fs04 document number: 38-07304 rev. *h page 2 of 15 contents pin configuration ............................................................. 3 failsafe function .............................................................. 4 xtal selection criteria and application example ...... 7 example ...................................................................... 7 absolute maximum conditions ....................................... 9 recommended pullable crystal specifications ............ 9 operating conditions for failsafe devices .................. 10 electrical characteristics for failsafe devices ........... 11 switching characteristics for failsafe devices .......... 11 ordering information ...................................................... 12 ordering code definition ........................................... 12 package diagram ............................................................ 12 acronyms ........................................................................ 13 document conventions ................................................. 13 units of measure ....................................................... 13 document history page ................................................. 14 sales, solutions, and legal information ...................... 15 worldwide sales and design s upport ......... .............. 15 products .................................................................... 15 psoc solutions ......................................................... 15
cy23fs04 document number: 38-07304 rev. *h page 3 of 15 pin configuration figure 1. pin diagram - cy23fs04 16-pin tssop table 1. pin definition pin no. pin name description 2, 1 ref[2:1] reference clock inputs. 5 v tolerant. [4] 4, 3 clkb[2:1] bank b clock outputs. [1,2] 13, 14 clka[2:1] bank a clock outputs. [1,2] 15 fbk feedback input to the pll. [1,4] 5, 12 s[2:1] frequency select pins and pll and dcxo bypass mode. [3] 8 xin reference crystal input. 9 xout reference crystal output. 10 fail#/safe valid reference indicator. a hi gh level indicates a valid reference input. 11 vdd 2.5 v or 3.3 v power supply. 7 vddc 3.3 v power supply. 6 vss ground. 16 refsel reference select. selects the active referenc e clock from either ref1 or ref2. refsel = 1, ref1 is selected; refsel = 0, ref2 is selected. table 2. configuration table s[2:1] xtal (mhz) ref (mhz) out (mhz) ref:out ratio ref:xtal ratio out:xtal ratio min max min max min max 00 pll and dcxo bypass mode 01 8.33 30.00 4.17 15.00 4.17 15.00 x1 1/2 1/2 10 8.00 25.00 16.00 50.00 16.00 50.00 x1 2 2 11 8.33 27.78 50.00 166.70 50.00 166.70 x1 6 6 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 cy23fs04 16 pin tssop ref1 ref2 clkb1 clkb2 vss vddc xin s2 refsel fbk clka1 clka2 s1 vdd fail#/safe xout notes 1. for normal operation, connect either one of the four clock outputs to the fbk input. 2. weak pull-downs on all outputs. 3. weak pull-ups on these inputs. 4. weak pull-down on these inputs
cy23fs04 document number: 38-07304 rev. *h page 4 of 15 failsafe function the cy23fs04 is targeted at cloc k distribution applications that require continued operation should the main reference clock fail. existing approaches to this requirement have used multiple reference clocks with either inte rnal or external methods to switch between references. the problem with this technique is that it leads to interruptions (o r glitches) when transitioning from one reference to another, often requiring complex external circuitry or software to mainta in system stability. the technique implemented in this design comple tely eliminates any switching of references to the pll, gr eatly simplifying system design. the cy23fs04 pll is driven by the crystal oscillator, which is phase-aligned to an external re ference clock so that the output of the device is effectively phase-aligned to the reference via the external feedback loop. this is accomplished by using a digitally controlled capacitor array to pull the crystal frequency over an approximate range of + 300 ppm from its nominal frequency. in this mode, if the reference frequency fails (stop or disappear), the dcxo maintains its last setting and a flag signal (fail#/safe) is set to indicate failure of the reference clock. the cy23fs04 provides two select bits, s1 and s2, to control the reference-to-crystal frequency ratio. the dcxo is internally tuned to the phase and frequency of the external reference only when the reference frequency divided by this ratio is within the dcxo capture range. if the freque ncy is out of range, a flag is set on the fail#/safe pin notifyi ng the system that the selected reference is not valid. if the reference moves in range, then the flag is cleared, indicating to the system that the selected reference is valid. figure 2. fail#/safe timing for in put reference failing catastrophically figure 3. fail#/safe timing formula table 3. failsafe timing table ref out fail#/safe t fsl t fsh n = f ref f xtal =4 (in above exam ple) t fsl(max) = 2 t ref x n ( ) + 25ns t fsh(min) = 12 t ref x n ( ) + 25ns parameter description conditions min max unit t fsl fail#/safe assert delay measured at 80% to 20%, load = 15 pf ? see figure 3 on page 4 ns t fsh fail#/safe assert delay measured at 80% to 20%, load = 15 pf see figure 3 on page 4 ?ns
cy23fs04 document number: 38-07304 rev. *h page 5 of 15 figure 4. failsafe timing diagram: input reference slowly drifting out of failsafe capture range figure 5. failsafe reference switching behavior reference + 300 ppm reference - 300 ppm reference output + 300 ppm output - 300 ppm output fail#/safe t fsh reference off t fsl time frequency volt
cy23fs04 document number: 38-07304 rev. *h page 6 of 15 because of the dcxo architecture, the cy23fs04 has a much lowe r bandwidth than a typical pll-based clock generator. this is shown in figure 6 . this low bandwidth makes the cy23fs04 also useful as a jitter attenuator. the loop bandwidth curve is also known as the jitter transfer curve. figure 6. failsafe effective loop bandwidth (min) figure 7. duty cycle figure 8. input slew rate figure 9. output slew rate t 1 t 2 duty cycle - t dc v dd /2 v dd /2 v dd /2 v dd 0v = t 1 / t 2 t sr(i) v dd 0v 30% 70% 70% 30% t sr(i) t sr(o) v dd 0v 20% 80% 80% 20% t sr(o)
cy23fs04 document number: 38-07304 rev. *h page 7 of 15 figure 10. output to output skew and intrabank skew figure 11. part to part skew figure 12. phase offset xtal selection criteria and application example choosing the appropriate xtal ensures the failsafe device is able to span an appropriate frequency of operation. also, the xtal parameters determine the holdover frequency stability. critical parameters are given here. cypress recommends that you choose: low c0/c1 ratio (240 or less) so that the xtal has enough range of pullability low temperature frequency variation low manufacturing frequency tolerance low aging c0 is the xtal shunt capacitance (3 pf to 7 pf typ). c1 is the xtal motional capacitance (10 ff to 30 ff typ). the capacitive load as ?seen? by the xtal is across its terminals. it is named c loadmin (for minimum value), and c loadmax (for maximum value).these are used to calculate the pull range. note that the c load range ?center? is approximately 20 pf, but you may not want a xtal calibrated to that load. this is because the pullability is not linear, as represented in the equation. plotting the pullability of the xt al shows this expected behavior as shown in figure 13 on page 8 . in this example, specifying a xtal calibrated to 16 pf load provides a balanced ppm pulla- bility range around the nominal frequency. example c loadmin = (12 pf ic input cap + 0 pf pulling cap + 6 pf trace cap on board) / 2 = 9 pf c loadmax = (12 pf ic input cap + 48 pf pulling cap + 6 pf trace cap on board) / 2 = 33 pf pull range = (fc loadmin ? fc loadmax ) / fc loadmin = (c1 / 2) * [(1 / (c0 + c loadmin )) ? (1 / (c0 + c loadmax ))] pull range in ppm = (c1 / 2) * [(1 / (c0 + c loadmin )) ? (1 / (c0 + c loadmax ))] * 10 6 v dd /2 v dd /2 t sk fbk, part 1 v dd /2 t sk(pp) v dd /2 fbk, part 2 ref v dd /2 t ( ? ) v dd /2 fbk
cy23fs04 document number: 38-07304 rev. *h page 8 of 15 figure 13. frequency vs. c load behavior for example xtal calculated value of the pullability range for the xtal with c 0 /c 1 ratio of 200, 250, and 300 are shown in ta b l e 4 on page 8. for this calculation, c loadmin = 7 pf and c load (max)= 31 pf is used. using a xtal that has a nominal frequency specified at load capacitance of 16 pf, almost symmetrical pullability range is obtained. next, it is important to calculate the pullability range including error tolerances. this is the capt ure range of the input reference frequency that the failsafe device and xtal combination can reliably span. calculating the capture range involves subtracting error tolerances as follows: parameter................................... ........................f error (ppm) manufacturing frequency toleranc e ...................................15 temperature stability ..........................................................30 aging ................................................................................... 3 board/trace variation ........................................................... 5 total ....................................................................................53 example: capture range for xt al with c0/c1 ratio of 200 negative capture range = ?300 ppm + 53 ppm = ?247 ppm positive capture range = 489 ppm ? 53 ppm = +436 ppm it is important to note that the xtal with lower c 0 /c 1 ratio has wider pullability/capture range as compared to the higher c 0 /c 1 ratio. this helps to select the appropriate xtal for use in the failsafe application. dcxo frequency vs. cload (normalized to 16pf cload) -400.00 -300.00 -200.00 -100.00 0.00 100.00 200.00 300.00 400.00 500.00 5 7 9 111315171921232527293133 cload (pf) delta freq. from nominal (ppm) c0/c1 = 200 c0/c1 = 250 c0/c1 = 300 table 4. pullability range from xtal with different c 0 /c 1 ratio c l calculated pull range in ppm, (normalized) (pf) c 0 /c 1 = 200 c 0 /c 1 = 250 c 0 /c 1 = 300 7 489.13 391.30 326.09 9 332.88 266.30 221.92 11 211.35 169.08 140.90 13 114.13 91.30 76.09 15 34.58 27.67 23.06 16 0.00 0.00 0.00 17 ?31.70 ?25.36 ?21.14 19 ?87.79 ?70.23 ?58.53 21 ?135.87 ?108.70 ?90.58 23 ?177.54 ?142.03 ?118.36 25 ?213.99 ?171.20 ?142.66 27 ?246.16 ?196.93 ?164.11 29 ?274.76 ?219.81 ?183.17 31 ?300.34 ?240.27 ?200.23
cy23fs04 document number: 38-07304 rev. *h page 9 of 15 important notes following are some important not es that should be considered when designing with the failsafe device: 1. the trace capacitance of the xtal inputs, xin and xout must be kept as small as possible. 2. specify the dcxo for c 0 /c 1 ratio to be less than 250 and the xtal load capacitance to be approximately 16 pf. a typical dcxo specification from ecliptek is attached here (please see page 6) for reference. 3. xtal with low temperature frequency variation, low manufacturing frequency tolerance and low aging must be chosen. 4. pull range must be checked for its upper and lower frequency symmetry from the nominal value as described in this application note. absolute maximum conditions exceeding maximum ratings may shorten the useful li fe of the device. user guidelines are not tested. parameter description condition min max unit v dd supply voltage ? ?0.5 4.6 v v in input voltage relative to v ss ?0.5 v dd +0.5 vdc t s temperature, storage n on functional ?65 150 c t j temperature, junction functional ? 125 c esd hbm esd protection (human body model) mil-std-883, method 3015 2000 ? v ? jc dissipation, junction to case mil-spec 883e method 1012.1 29.87 c/w ? ja dissipation, junction to ambient jedec (jesd 51) 120.11 c/w ul?94 flammability rating at 1/8 in. v?0 msl moisture sensitivity level ? 3 multiple supplies: the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supp ly sequencing is not required. recommended pullable crystal specifications [5] parameter name comments min typ max unit f nom nominal crystal frequency parallel resonance, fundamental mode, at cut 8.00 ? 30.00 mhz c loadnom nominal load capacitance ? 14 ? pf r 1 equivalent series resistance (esr) fundamental mode ? ? 25 ? r 3 /r 1 ratio of third overtone mode esr to funda- mental mode esr ratio used because typical r 1 values are much less than the maximum spec 3?? dl crystal drive level no external series resistor assumed ? 0.5 2 mw f 3sepli third overtone separation from 3*f nom high side 300 ? ? ppm f 3seplo third overtone separation from 3*f nom low side ? ? ?150 ppm c0 crystal shunt capacitance ? ? ? 7 pf c0 / c1 ratio of shunt to motional capacitance ? 180 ? 250 c1 crystal motional capacitance ? 14.4 18 21.6 ff
cy23fs04 document number: 38-07304 rev. *h page 10 of 15 operating conditions for failsafe devices parameter description min max unit v ddc 3.3-v supply voltage 3.135 3.465 v v dd 2.5-v supply voltage range 2.375 2.625 v 3.3-v supply voltage range 3.135 3.465 v t a ambient operating temper ature, commercial 0 70 c ambient operating temperat ure, industrial ?40 85 c c l output load capacitance (fout < 100 mhz) ? 30 pf output load capacitance (fout > 100 mhz) ? 15 pf c in input capacitance (except xin) ? 7 pf c xin crystal input capacitance (all internal caps off) 10 13 pf t pu power-up time for all v dd s to reach minimum specified voltage (power ramps must be monotonic) 0.05 500 ms note 5. ecliptek ecx-5788-13.500m, ecx-5807-19.440m, ecx-5872-19.53125m , ecx-6362-18.432m, ecx-5808-27.000m, ecx-5884-17.664m, ecx-58 83-16.384m, ecx-5882-19.200m, ecx-5880-24.576 m meet these specifications.
cy23fs04 document number: 38-07304 rev. *h page 11 of 15 electrical characteristi cs for failsafe devices parameter description test conditions min typ max unit v il input low voltage cmos levels, 30% of v dd ? ? 0.3 v dd v v ih input high voltage cmos levels, 70% of v dd 0.7 v dd ?v i il input low current v in = v ss (100k pull up only) ? ? 50 a i ih input high current v in = v dd (100k pull down only) ? ? 50 a i ol output low current v ol = 0.5 v, v dd = 2.5 v ? 18 ? ma v ol = 0.5 v, v dd = 3.3 v ? 20 ? ma i oh output high current v oh = v dd ? 0.5 v, v dd = 2.5 v ? 18 ? ma v oh = v dd ? 0.5 v, v dd = 3.3 v ? 20 ? ma i ddq quiescent current all inputs grounded, pll and dcxo in bypass mode, reference input = 0 ? ? 250 a switching characteristics for failsafe devices parameter [7] description test conditions min max unit f ref reference frequency commercial/i ndustrial grades 4.17 166.7 mhz f out output frequency 15 pf load, commercial/industrial grades 4.17 166.7 mhz f xin dcxo frequency 8.0 30 mhz t dc duty cycle measured at v dd /2 47 53 % t sr(i) input slew rate measured on re f1 input, 30% to 70% of v dd 0.5 4.0 v/ns t sr(o) output slew rate measured from 20% to 80% of v dd = 3.3 v, 15 pf load 0.8 4.0 v/ns measured from 20% to 80% of v dd = 2.5 v, 15 pf load 0.4 3.0 v/ns t sk(o) output-to-output skew all outputs equally loaded, measured at v dd /2 ? 200 ps t sk(pp) part-to-part skew measured at v dd /2 ? 500 ps t ( ? ) [6] static phase offset measured at v dd /2 ? 250 ps t d( ? ) [6] dynamic phase offset measured at v dd /2 ? 500 ps t j(cc) cycle-to-cycle jitter load = 15 pf, f out ?? 6.25 mhz ? 200 ps ?35ps rms notes 6. the t ( ?? reference feedback input delay is guaranteed for a maximum 4:1 input edge ratio between the two signals as long as t sr(i) is maintained. static phase offset excludes jitter; dynamic phase offset includes jitter. 7. parameters guaranteed by design and characterization, not 100% tested in production
cy23fs04 document number: 38-07304 rev. *h page 12 of 15 ordering code definition package diagram figure 14. 16-pin tssop 4.40 mm body ordering information part number package type product flow pb-free cy23fs04zxi 16-pin tssop industrial, ?40 c to 85 c cy23fs04zxit 16-pin tssop ? tape and reel industrial, ?40 c to 85 c CY23FS04ZXC 16-pin tssop commercial, 0 c to 70 c CY23FS04ZXCt 16-pin tssop ? tape and reel commercial, 0 c to 70 c cy23fs04 package type: t = tape and reel, blank = tube temperature code: c = commercial; i = industrial package: 16-pin tssop, pb-free device number zx x (t) 51-85091 *d
cy23fs04 document number: 38-07304 rev. *h page 13 of 15 acronyms document conventions units of measure acronym description dcxo digitally controlled crystal oscillator esd electrostatic discharge pll phase locked loop rms root mean square ssop shrunk small outline package tsspo thin shrunk sm all outline package xtal crystal symbol unit of measure ? c degree celsius a microampere ma milliampere ms milli second mhz megahertz ns nanosecond pf picofarad ps picosecond vvolt
cy23fs04 document number: 38-07304 rev. *h page 14 of 15 document history page document title: cy23fs04 failsafe? 2.5 v/3.3 v zero delay buffer document number: 38-07304 revision ecn submission date orig. of change description of change ** 123698 04/24/03 rgl new data sheet *a 223811 see ecn rgl/zjx changed the xtal specifications table. *b 276712 see ecn rgl removed (t lock ) lock time specification *c 378918 see ecn rgl added lead-free devices *d 2865337 01/25/2010 cxq updated format. changed max output frequency from 170 mhz to 166.7 mhz. added ?contents? section on page 2. removed previous figures 5 and 6. added/separated figures 7 through 12. changed references of ?cl? to ?c load ?. removed extra t a reference in absolute maximum conditions. changed table captions for tables 4, 5, and 6 to section headings. removed note 5 regarding programming cap array. replaced crystal ecx?5806?18.432m with ecx?6362?18.432m in note 5. removed obsolete/pruned pb-devic es from ordering information. removed unreferenced note 9. updated package drawing specification to rev *b. *e 2925613 04/30/10 kvm posting to external web. *f 3054919 10/11/2010 kvm revised dynamic phase offset value. added phase offset definition. updated package diagram . added acronyms , document conventions , and ordering code definition *g 3342812 08/12/2011 puru updated ordering code definition . *h 3695677 08/03/2012 puru updated figure 13 and ta b l e 4 . revised package diagram to *d. added section important notes . changed ssop to tssop in ordering code definition .
document number: 38-07304 rev. *h revised august 8, 2012 page 15 of 15 failsafe? is a trademark of cypress semiconductor corporation. purchase of i 2 c components from cypress or one of its sublicensed a ssociated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. as from october 1st, 2006 philips semiconductors has a new trade name - nxp semiconductors. all products and company names mentioned in this document may be the trademarks of t heir respective holders. cy23fs04 ? cypress semiconductor corporation, 2003-2012. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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